1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a multibit memory for inputting and outputting data in a unit of bits.
2. Description of the Related Art
Semiconductor memory devices have a memory cell array from which a memory cell can be selected by designating a row address and a column address. Unless specially designed otherwise, data are inputted to and outputted from the memory cell array bit by bit. In a CPU to which such a semiconductor memory device is connected, one word is composed of plural bits, e.g., 16 bits or 32 bits, and data are inputted to and outputted from the CPU word by word. Since using as many semiconductor memory devices as the number of bits on a data bus connected to a CPU is limited by cost and package area considerations, there have widely been developed semiconductor memory devices capable of inputting and outputting data in a unit of simultaneous parallel bits.
A semiconductor memory device for inputting and outputting data in a unit of bits will hereinafter be referred to as a "multibit memory", and a bit serving as a unit for inputting and outputting data will hereinafter be referred to as an "IO bit". A multibit memory has as many data input/output terminals as the number of IO bits, and each data input/output terminal is used to input and output 1-bit data. Data are written in and read from a multibit memory in a parallel fashion through the data input/output terminals. Typically, the number of the IO bits is 4, 8 or 16.
Generally, a memory cell array of a multibit memory may be divided per IO bit, or may be arranged to correspond to a plurality of different IO bits. In former memory cell array configuration, the number of IO bits is limited by the number of divisions of the word length of the memory cell array. For example, if the word length is divided into four sections, then the memory cell array is divided into four memory cell arrays, and these four memory cell arrays can be accessed simultaneously. When different IO bits are assigned respectively to the four memory cell arrays, the memory cell arrays jointly make up a memory whose IO bits are four bits. The number of divisions of the word length is generally determined in view of the time constant of word lines. If a word length is divided into halves, then the number of memory cells connected to a word line is reduced to one-half, and the length of the line is reduced to one-half, with the result that the time constant becomes one-quarter. Therefore, the number of divisions of a word line is determined so that the time constant thereof will satisfy the access speed for a target word line.
If a word length is divided into quarters, then a memory cell array is divided into four memory cell arrays, making it possible to construct a memory of IO bits up to four bits. However, it is impossible to construct a memory having more IO bits without mixing different IO bits in the same memory cell array. Stated otherwise, in order to construct a memory having eight IO bits, it is necessary to distribute two IO bits, i.e., two data input/output terminals, to each memory cell array.
FIG. 1 shows in block form a conventional multibit dynamic memory, the view primarily illustrating an input/output circuit thereof. For the sake of brevity, the memory circuit has two IO bits. One memory cell array 100 has memory cells MC.sub.11 to MC.sub.14, MC.sub.21 to MC.sub.24 each belonging to a different IO bit (input/output signal terminals IO.sub.1, IO.sub.2).
The input/output signal terminals IO.sub.1, IO.sub.2 are data terminals which will be used to input and output data to and from the memory cells. The input/output signal terminals IO.sub.1, IO.sub.2 are connected to input buffers DIN.sub.1, DIN.sub.2, respectively, and output buffers DOUT.sub.1, DOUT.sub.2, respectively. The memory has data buses RWBS.sub.1, RWBS.sub.2. The data bus RWBS.sub.1 is connected through buffers 91, 93 respectively to the input buffer DIN.sub.1 and the output buffer DOUT.sub.1, and the data bus RWBS.sub.2 is connected through buffers 92, 94 respectively to the input buffer DIN.sub.2 and the output buffer DOUT.sub.2. To the data buses RWBS.sub.1, RWBS.sub.2, there are connected respective write data amplifiers WBUF.sub.1, WBUF.sub.2 and respective read data amplifiers DAMP.sub.1, DAMP.sub.2.
The memory has input/output data line pairs IOT.sub.1 /ION.sub.1, IOT.sub.2 /ION.sub.2 near the memory cell array. The input/output data line pairs IOT.sub.1 /ION.sub.1 are connected to both of the write data amplifier WBUF.sub.1 and the read data amplifiers DAMP.sub.1, and the input/output data line pairs IOT.sub.2 /ION.sub.2 are connected to both of the write data amplifier WBUF.sub.2 and the read data amplifiers DAMP.sub.2.
The memory cell array 100 has word lines WL.sub.1, WL.sub.2, . . . and digit line pairs DL.sub.1 /DL.sub.i, DL.sub.2 /DL.sub.2, DL.sub.3 /DL.sub.3, . . . which extend perpendicularly to each other. Memory cells MC.sub.11, MC.sub.12, MC.sub.13, MC.sub.14, MC.sub.21, MC.sub.22, . . . positioned at the respective points of intersection between the word lines and the digit line pairs. Sense amplifiers S.sub.1, S.sub.2, S.sub.3, S.sub.4, . . . including column switches are provided at ends of the respective digit line pairs DL.sub.1 /DL.sub.1, DL.sub.2 /DL.sub.2, DL.sub.3 /BL.sub.3, . . . . The odd-numbered sense amplifiers S.sub.1, S.sub.3, . . . are connected to the input/output data line pairs IOT.sub.1 /ION.sub.1, and the even-numbered sense amplifiers S.sub.2, S.sub.4, . . . are connected to the input/output data line pairs IOT.sub.2 /ION.sub.2. The sense amplifiers S.sub.1, S.sub.2, S.sub.3, S.sub. 4, . . . are activated by column switch signals to connect corresponding digit line pairs and input/output data line pairs. Each of the column switch signals corresponds to two sense amplifiers, so that sense amplifiers S.sub.2n-1, S.sub.2n can be controlled by a column switch signal YSW.sub.n.
Operation of the multibit memory shown in FIG. 1 will be described below.
In a write operation mode, external signal levels applied to the input/output signal terminals IO.sub.1, IO.sub.2 are supplied through the input buffers DIN.sub.1, DIN.sub.2 and the buffers 91, 92 to the data buses RWBS.sub.1, RWBS.sub.2, respectively. In a read operation mode, data from the data buses RWBS.sub.1, RWBS.sub.2 are outputted through the buffers 93, 94 and the output buffers DOUT.sub.1, DOUT.sub.2 to the input/output signal terminals IO.sub.1, IO.sub.2.
Data are written in and read from the memory cell array 100 through the input/output data line pairs IOT.sub.1 /ION.sub.1, IOT.sub.2 /ION.sub.2, the write data amplifiers WBUF.sub.1, WBUF.sub.2, and the read data amplifiers DAMP.sub.1, DAMP.sub.2. More specifically, data are written in the memory cell array 100 as follows: Data supplied to the data buses RWBS.sub.1, RWBS.sub.2 are amplified by the write data amplifiers WBUF.sub.1, WBUF.sub.2, and then supplied to the input/output data line pairs IOT.sub.1 /ION.sub.1, IOT.sub.2 /ION.sub.2, respectively. When either one of the column switch signals YSW.sub.1, YSW.sub.2, . . . is activated by a column address signal, the corresponding sense amplifier is activated. For example, if the column switch signal YSW.sub.1 is selected and activated, then data supplied to the input/output data line pair IOT.sub.1 /ION.sub.1 are outputted through the sense amplifier S.sub.1 to the digit line pair DL.sub.1 /DL.sub.1, and data supplied to the input/output data line pair IOT.sub.2 /ION.sub.2 are outputted through the sense amplifier S.sub.2 to the digit line pair DL.sub.2 /DL.sub.2.
At the same time, either one of the word lines WL.sub.1, WL.sub.2, is activated by a row address signal, thereby writing the data on the digit lines in the connected memory cells. For example, if the word line WL.sub.1 is selected and activated, then the data supplied to the digit line pairs DL.sub.1 /DL.sub.1, DL.sub.2 /DL.sub.2 are written in the respective memory cells MC.sub.11, MC.sub.12.
Data stored in the memory cell array 100 are read as follows:
If the word line WL.sub.1 is selected and activated, then data stored in the memory cells MC.sub.11, MC.sub.12, MC.sub.13, MC.sub.14 are supplied respectively to the digit lines DL.sub.1, DL.sub.2, DL.sub.3, DL.sub.4 and amplified respectively by the sense amplifiers S.sub.1, S.sub.2, S.sub.3, S.sub.4. If, at this time, the column switch signal YSW.sub.1 is selected and activated, then data from the digit line pair DL.sub.1 /DL.sub.1 are outputted to the input/output data line pair IOT.sub.1 /ION.sub.1 through the sense amplifier S.sub.1 and data from the digit line pair DL.sub.2 /DL.sub.2 are outputted to the input/output data line pair IOT.sub.2 /ION.sub.2 through the sense amplifiers S.sub.2. These data are then amplified by the read data amplifiers DAMP.sub.1, DAMP.sub.2 and outputted to the data buses RWBS.sub.1, RWBS.sub.2.
In the memory shown in FIG. 1, each of the memory cells of the memory cell array 100 corresponds to either one of the first and second input/output signal terminals IO.sub.1, IO.sub.2. Specifically, data are inputted to and outputted from the memory cells MC.sub.11, MC.sub.13, MC.sub.21, MC.sub.23, . . . only through the first-input/output signal terminal IO.sub.1, and data are inputted to and outputted from the memory cells MC.sub.12, MC.sub.14, MC.sub.22, MC.sub.24, . . . only through the second input/output signal terminal IO.sub.2. Consequently, data are inputted to and outputted from the memory cells MC.sub.11, MC.sub.12, for example, through different paths, and data are inputted to and outputted from the memory cells MC.sub.13, MC.sub.14, or MC.sub.21, MC.sub.22, or MC.sub.23, MC.sub.24 through different paths.
For testing the memory, it is necessary to write data in the memory cells of the memory cell array in various patterns. A process of writing of data for testing the memory will be described below.
First, logic level "0" is to be written in all of the memory cells MC.sub.11, MC.sub.12, MC.sub.13, MC.sub.14, . . . on the word line WL.sub.1. It is assumed that the input/output signal terminals IO.sub.1, IO.sub.2 and the data buses RWBS.sub.1, RWBS.sub.2 are of positive logic through the input buffers DIN.sub.1, DIN.sub.2 and the buffers 91, 92, the data buses RWBS.sub.1, RWBS.sub.2 and the input/output data lines IOT.sub.1, IOT.sub.2 are of positive logic through the write data amplifiers WBUF.sub.1, WBUF.sub.2, the data buses RWBS.sub.1, RWBS.sub.2 and the input/output data lines ION.sub.1, ION.sub.2 are of negative logic through the write data amplifiers WBUF.sub.1, WBUF.sub.2, and the input/output data line pairs and the digit line pairs are of positive logic through the sense amplifier. When logic level "0" is given to the input/output signal terminals IO.sub.1, IO.sub.2, therefore, the data buses RWBS.sub.1, RWBS.sub.2 are set to logic level "0", the input/output data lines IOT.sub.1, IOT.sub.2 to logic level "0", the input/output data lines ION.sub.1, ION.sub.2 to logic level "1", the digit lines DL.sub.1, DL.sub.2 to logic level "0", and the digit lines DL.sub.1, DL.sub.2 to logic level " 1". Accordingly, logic level "0" on the digit lines DL.sub.1, DL.sub.2 is given to the memory cells MC.sub.11, MC.sub.12. In order to write logic level "0" in all the memory cells on the word line WL.sub.1, logic level "0" may be given to both the input/output signal terminals IO.sub.1, IO.sub.2, an address corresponding to the word line WL.sub.1 may be given to a row address signal, and a column address signal may successively be changed.
Then, data which are of reversed logic levels in adjacent memory cells are to be written in the memory cells on the word line WL.sub.1. Those memory cells which are adjacent to each other on the word line WL.sub.1 are memory cells belonging to different IO bits (input/output signal terminals IO.sub.1, IO.sub.2). Therefore, in order to write data which are of different logic levels in adjacent memory cells, logic levels "0", "1" or "1", "0" are given to the respective input/output signal terminals IO.sub.1, IO.sub.2, and column addresses are successively changed.
A data pattern of "0", "1", "1", "0" is to be written in the memory cells on a word line, i.e., data of logic level "0", logic level "1", logic level "1", and logic level "0" are to be written respectively in the memory cells MC.sub.11, MC.sub.12, MC.sub.13, MC.sub.14. In order to write logic levels "0", "1" respectively in the memory cells MC.sub.11, MC.sub.12, an address corresponding to the word line WL.sub.1 is given to a row address signal, an address for selecting and activating the column switch signal YSW.sub.1 is given to a column address signal, and logic levels "0", "1" are given to the respective input/output signal terminals IO.sub.1, IO.sub.2. Then, in order to write logic levels "1", "0" respectively in the memory cells MC.sub.13, MC.sub.14, an address corresponding to the word line WL.sub.1 is given to the row address signal, an address for selecting and activating the column switch signal YSW.sub.2 is given to the column address signal, and logic levels "1", "0" are given to the respective input/output signal terminals IO.sub.1, IO.sub.2. At this time, it is necessary to vary, with a column address of the memory cell which is to be accessed, a combination of logic levels to be given to the input/output signal terminals IO.sub.1, IO.sub.2.
Writing data patterns in the memory cells on a word line has been described. Dynamic memories must be tested using such various data patterns, and a requirement is that they can be checked easily by such a test.
Japanese patent Laid-Open No. 191400/1988 (JP, A 63-191400) discloses a multibit memory which can be tested using only one data input/output signal terminal by degenerating the contents of a function-test from a plurality of memory cells to one signal. The disclosed multibit memory is effective to reduce the number of comparators that are required to test the multibit memory.
A dynamic memory in which memory cells corresponding to different IO bits are mixed in one memory cell array needs to take into account the relationship between the logic addresses of memory cells and physical positions thereof (hereinafter referred to as "physical addresses") and also information about which IO bit each memory cell belongs to, at the time a complex data pattern is to be written in memory cells.
A memory tester is used to test a memory. Such a memory tester generally has a scrambling function for converting logic addresses into physical addresses. However, memory testers having a scrambling function which takes into consideration IO bits in multibit memories are rarely available. Therefore, conventional multibit memories cannot be tested thoroughly insofar as an ordinary memory tester is used. It is not easy to generate a data pattern for use in a memory test, with IO bits taken into account.